Semiconductor device geometries have dramatically decreased in size since their introduction decades ago. Modern semiconductor fabrication equipment routinely produces devices with 45 nm, 32 nm, and 28 nm feature sizes, and new equipment is being developed and implemented to make devices with even smaller geometries. The decreasing feature sizes result in structural features on the device having decreased spatial dimensions. The widths of gaps and trenches on the device have narrowed to a point where the aspect ratio of gap depth to width becomes high enough to make it challenging to fill the gap with dielectric material. Additionally, the portions of the substrate remaining between the gaps and separating them are becoming even thinner.
When dielectric materials are deposited within and over these gaps, they affect the underlying substrate. For example, when a curing operation is performed, some dielectric materials will shrink to an extent, or densify, which may produce a force on the underlying substrate. When gaps of differing widths lie adjacent to one another, unequal forces may be imposed on opposite sides of the divide based on the amount of deposited material.
Thus, there is a need for new fabrication processes and materials that may adequately fill substrate gaps, while maintaining the substrate feature profiles. These and other benefits are provided by the disclosed technology.